In electronic apparatus, as progress in downsizing, or the making of the overall apparatus smaller, continues the considerations that must be met in the package for the semiconductor chip become greater. The package must not only support the chip and protect from deleterious environmental contaminants but it must also maintain reliable and easily attachable connections to external circuitry through ever widening temperature cycling as the number of devices in the chip increase. The increasing of the density in the chip results in smaller and more closely spaced pads and in turn more fragile conductor connections result.
A current chip packaging technique employs a lead frame type structure of dielectric supported conductors with close spacing at a central aperture and more relaxed spacing at external connectors around the periphery. The chip is fastened to the lead frame at the central aperture and delicate leads are employed to join the close spaced lead frame conductors to the pads on the chip. The chip and the lead frame are encapsulated in a dielectric body. Such a packaging structure is described in U.S. Pat. No. 4,862,245.
As more stringent performance specifications are encountered, a need is developing for a package that reduces the effects of mechanical stresses from material mismatches, that reduces damage to the fragile leads joining the chip pads to the package wiring, that maintains optimum electrical signal transmission properties closer to the pads and with a minimal increase in overall dimensions after encapsulation.